The basic idea of producing logic signal displays for a digital input signal by sampling the digital input signal as an analog signal to produce multi-bit digital samples which are then processed to determine logic states over time is outlined in U.S. Pat. Nos. 5,446,650 and 5,854,996, both entitled “Logic Signal Extraction”. The “logic oscilloscope” to which these patents relate is the Tektronix TLS216, manufactured by Tektronix, Inc. of Beaverton, Oreg. In this instrument, sixteen (16) input channels are first rapidly sampled and the analog data is stored in a capacitor array of a FISO (Fast-In/Slow-Out) circuit. Later, the data in the capacitor array is digitized at a slower rate and stored in a memory having a record length of up to two thousand (2,000) samples. After the acquisition operation is completed, the records are then processed with software using one or more threshold values to produce logic waveforms for display.
One disadvantage of this scheme is that putting digitized data into memory is very inefficient compared to typical memory contents of a logic analyzer. A logic analyzer may store a single bit per channel per data clock cycle, whereas the TLS216 stores a byte per channel per sample clock cycle. There may be many sample clocks per data clock, making memory use many times less efficient because much more data has to be stored.
Another disadvantage of this scheme is that certain common types of logic analyzer triggers use the logic level of the input signals. To obtain common logic analyzer trigger modes, an instrument uses traditional logic analyzer signal comparators. However, it is not possible with this architecture to use the digitized data in the trigger circuitry because the digitized data is only available after a trigger has been detected and the acquisition process is completed.
The concept of real-time processing of acquired information is presented in U.S. Pat. No. 5,526,286 entitled “Oversampled Logic Analyzer”. This scheme is currently being used in Tektronix logic analyzer products, such as the TLA5000 and TLA7000 series. The input signals are sampled at a rate that is very fast for the technology being analyzed, i.e., many times faster than the data clock. The data, which is in the form of one-bit samples, is then processed in parallel. The high sample rate results in good time resolution, but the data is inefficiently coded. The sample rate is much higher than the Nyquist frequency of the signals being analyzed. The coding efficiency is greatly improved by a re-sampling operation using the data clock. Channels designated as clock channels are used to find the times of edge transitions. These times are then used to re-sample the other channels. After the re-sampling operation, the logic state of the data channels is written into a deep memory along with a time stamp.
The '286 patent works with the deep memory, and is compatible with traditional logic analyzer triggering modes. It also provides much better timing resolution than that provided by the data clock. However, it does not allow for correction of the signal fidelity, and it does not support a way to view the analog waveform.
What is desired is a scheme for implementing a logic analyzer that allows for correction of the signal fidelity, allows a display of an analog waveform, and allows for the re-sampling of the data based on the data clock so that an efficient coding of the state of the data lines may be stored in a deep memory.